Ever since the 90 nm CMOS integrated circuit technology, with the continuous reduction in the feature size of the device, the Strain Channel Engineering for the purpose of increasing the carrier mobility in the channel region is playing a more important role continuously. The carrier mobility can be effectively increased by introducing a stress into the channel region using a technology, so that the driving capability of the device can be enhanced.
As shown in Table 1 below, many researches have proved that there is a great difference between the piezoresistance coefficients of the NMOS and PMOS devices having channel regions with <110> crystal orientation on a (001) wafer, wherein the unit of the piezoresistance coefficient is 10−12 cm2/dyn.
(001) wafer<100><100><110><110>polarityπ∥π⊥π∥π⊥π11π12(π11 + π12 + (π11 + π12 − π44)/2π44)/2n-MOSFET−42.6/−102 −20.7/53.4  −35.5/−31.6−14.5/−17.6p-MOSFET9.1/6.6−6.2/−1.171.7/71.8−33.8/−66.3
It can be seen that, in the direction of the width of the channel, i.e. in the direction of the horizontal axis, a tensile stress can improve the performance of both the NMOS and PMOS devices when the channel direction is <110> direction on the (001) wafer. In the direction of the length of the channel, i.e. in the direction of the vertical axis, it is preferable to use a different type of stress, such as a compressive stress, between the NMOS and PMOS devices when the channel direction is <110> direction on the (001) wafer. Therefore, the NMOS and PMOS devices can theoretically be manufactured by forming active regions (well regions) with different crystal orientations on the (001) wafer substrate, respectively, so that each of the MOSFETs has either a tensile stress or a compressive stress, thereby effectively increasing the carrier mobility. However, such a method requires extra complicated processes, for example, epitaxying active regions and well regions with different crystal orientations on the substrate, respectively, which prolong the process time and increase the manufacturing cost.
Another solution that is theoretically feasible is to apply a stress to the channel region by means of a stress occurring at the contact interface between different materials, especially materials with different crystal structures. As an example, a compressive stress and a tensile stress are caused by a mismatch between the crystal lattices of the substrate Si and the source region SiGe and between the crystal lattices of the substrate Si and the drain region SiC, respectively, which applies to the PMOS and NMOS devices. Likewise, in this solution, extra steps of etching the substrate to form trenches and performing epitaxial growth are required, which results in high cost.
Furthermore, a strained channel is formed before depositing a gate, and such stress may remain in the channel region after removing a stressed layer of shallow trench isolation (STI), that is, the gate can be used for memorizing (i.e., storing) the stress. Thus, it is desired that a stress may be applied to the channel region by appropriately designing and manufacturing the STI.
In summary, the existing methods for introducing a stress into the channel region may result in a complicated process and high cost.